The present invention relates generally to signal converting or receiving circuits and, more particularly, to a CMOS (complementary metal-oxide-semiconductor) circuit for receiving ECL (emitter coupled logic) signals and converting them into CMOS signals for use in a related CMOS circuit.
Many current computer systems are implemented using more than one hardware technology in order to achieve better cost versus performance ratios. For example, it is not uncommon to find both CMOS and ECL circuits used in one computer system. CMOS circuits are typically used where cost, density and/or power consumption are important considerations since CMOS technology permits higher levels of integration, consumes less power and is less expensive. On the other hand, ECL circuits are used where high switching speeds are required.
A problem with implementing a computer system with more than one hardware technology, such as with CMOS and ECL, is that the same logic signal levels within the circuits are represented by different voltage levels. For example, in a CMOS circuit, a logic level "1" will commonly be represented by ground or zero potential and a corresponding logic level "0" will be represented by 5.0 V. In comparison, for an ECL circuit a logic level "1" may be represented by -0.95 V and a logic level "0" may be represented by -1.72 V. It is thus necessary to provide signal converters or receivers which interface signals from an ECL circuit to a CMOS circuit and vice versa.
Such signal receivers also contribute to higher operating speeds for CMOS circuits even where there are no ECL circuits used in a system. As the clock speeds of CMOS systems approach 100 MHz, many CMOS systems have adopted ECL logic levels at chip interfaces to reduce chip-to-chip crossing delays. By adopting ECL logic levels at the interfaces between CMOS chips, the voltage swings are much smaller and terminated transmission line networks provide shorter signal settling times. For example, many CMOS SRAMs (static random access memories) have been designed with ECL interfaces to achieve faster access times. In these and other similar cases, ECL signal receivers (ECL to CMOS) and CMOS signal receivers (CMOS to ECL) are needed even though an entire system is composed of CMOS circuits.
An example of a CMOS to ECL signal converter circuit or CMOS receiver circuit is illustrated in U.S. Pat. No. 5,047,671 which is assigned to the same assignee as the present application. A conventional prior art CMOS circuit 100 for receiving ECL signals, VIN, and converting the ECL signals to CMOS signals, VOUT, is illustrated in FIG. 1 and comprises a differential amplifier circuit 102 followed by an inverter circuit 104. Unfortunately, the conventional CMOS circuit 100 is highly susceptible to variations in the CMOS manufacturing process, operating temperature and voltage level of the power supply which variations lead to shifts in the transfer characteristics and resulting degradation in the sensitivity of the receiver. This sensitivity degradation substantially reduces the noise margin of the receiver since the voltage swings of the ECL logic levels are so small.
Accordingly, there is a need for an improved performance CMOS circuit for receiving ECL signals wherein the transfer characteristics are less susceptible to variations in the manufacturing process, operating temperature and power supply levels. Preferably, the improved performance CMOS circuit would include transfer characteristics which remain substantially symmetric around a logic level defining reference voltage.